IEEE - Institute of Electrical and Electronics Engineers, Inc. - Test pattern generation for power supply droop faults

Proceedings. 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems and Design

Author(s): D. Mitra ; S. Bhattacharjee ; S. Sur-Kolay ; B.B. Bhattacharya ; S.T. Zachariah ; S. Kunduc
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Hyderabad, India, India
Conference Date: 3 January 2006
ISBN (Paper): 0-7695-2502-4
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSID.2006.158
Regular:

In deep sub-micron VLSI chips, when several transistors in physical proximity switch simultaneously, a substantial power supply drop, known as droop, may occur because of concurrent load on a via... View More

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