IEEE - Institute of Electrical and Electronics Engineers, Inc. - A comprehensive solution for true hierarchical timing and crosstalk delay signoff

Proceedings. 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems and Design

Author(s): K.A. Rajagopal ; R. Sivakumar ; N.V. Arvind ; C. Sreeram ; V. Visvanathan ; S. Dhuri ; R. Chander ; P. Fortner ; S. Sripada ; Qiuyang Wu
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Hyderabad, India, India
Conference Date: 3 January 2006
ISBN (Paper): 0-7695-2502-4
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSID.2006.8
Regular:

Leading edge technology advancements have posed big challenges for the digital design flow. Designing multi-million gate ICs at aggressive cycletimes requires new design methodologies and... View More

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