IEEE - Institute of Electrical and Electronics Engineers, Inc. - CAD tools for a globally asynchronous locally synchronous FPGA architecture

Proceedings. 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems and Design

Author(s): Xin Jia ; R. Vemuri
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Hyderabad, India, India
Conference Date: 3 January 2006
ISBN (Paper): 0-7695-2502-4
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSID.2006.54
Regular:

The performance of FPGAs is suffering from interconnect delays, especially the delays of the long wires which can be more than 10ns in large FPGAs. We have proposed the GAPLA: a globally... View More

Advertisement