IEEE - Institute of Electrical and Electronics Engineers, Inc. - Reducing design verification cycle time through testbench redundancy

Proceedings. 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems and Design

Author(s): A. Kokrady ; R. Mehrotra ; T.J. Powell ; S. Ramakrishnan
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Hyderabad, India, India
Conference Date: 3 January 2006
ISBN (Paper): 0-7695-2502-4
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSID.2006.140
Regular:

Design flows for modern-day system-on-chip (SoC) designs focus on reducing the design cycle time, but not on design verification time. Nearly 70% of SoC design cycle time is consumed by design... View More

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