IEEE - Institute of Electrical and Electronics Engineers, Inc. - A low cost, high quality embedded array DFT technique for high performance processors

Third IEEE International Workshop on Electronic Design, Test and Applications

Author(s): Z. Bao ; S.A. Kumar ; D.M. Wu ; V.K. Natarajan ; M. Lin
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Kuala Lumpur, Malaysia
Conference Date: 17 January 2006
ISBN (Paper): 0-7695-2500-8
DOI: 10.1109/DELTA.2006.5
Regular:

This paper describes a low cost, high quality array DFT technique that will save overall manufacturing test time by /spl sim/50%. This technique integrates a programmable on-die test generation... View More

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