IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 4/sup th/-order 86dB CT /spl Delta//spl Sigma/ ADC with two amplifiers in 90nm CMOS

2005 IEEE International Solid-State Circuits Conference

Author(s): A. Das ; R. Hezar ; R. Byrd ; G. Gomez ; B. Haroun
Sponsor(s): IEEE Solid-State Circuits Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: San Francisco, CA, USA
Conference Date: 10 February 2005
Page Count: 3
ISBN (Paper): 0-7803-8904-2
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.2005.1494086
Regular:

A fourth-order 1b CT /spl Delta//spl Sigma/ converter using a two-amplifier loop and a 267MHz sampling frequency is implemented in 90nm CMOS. A double-loop architecture couples passive poles with... View More

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