IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a CELL processor

2005 IEEE International Solid-State Circuits Conference

Author(s): S.H. Dhong ; O. Takahashi ; M. White ; T. Asano ; T. Nakazato ; J. Silberman ; A. Kawasumi ; H. Yoshihara
Sponsor(s): IEEE Solid-State Circuits Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: San Francisco, CA, USA
Conference Date: 10 February 2005
Page Count: 3
ISBN (Paper): 0-7803-8904-2
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.2005.1494081
Regular:

A 6-stage fully pipelined embedded SRAM is implemented in a 90nm SOI technology. The array uses a conventional 6-transistor memory cell and sense amplifier to achieve the cycle time while... View More

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