IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 3-GHz 70MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply

2005 IEEE International Solid-State Circuits Conference

Author(s): K. Zhang ; U. Bhattacharya ; Z. Chen ; F. Hamzaoglu ; D. Murray ; N. Vallepalli ; Y. Wang ; B. Zheng ; M. Bohr
Sponsor(s): IEEE Solid-State Circuits Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: San Francisco, CA, USA
Conference Date: 10 February 2005
Page Count: 3
ISBN (Paper): 0-7803-8904-2
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.2005.1494075
Regular:

A 70MB SRAM chip is designed and fabricated in 65nm CMOS technology. A column-based dynamic multi-V, scheme is integrated into the design to improve cell read and write margins while reducing... View More

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