IEEE - Institute of Electrical and Electronics Engineers, Inc. - 0.94ps-rms-jitter 0.016mm/sup 2/ 2.5GHz multi-phase generator PLL with 360/spl deg/ digitally programmable phase shift for 10Gb/s serial links

2005 IEEE International Solid-State Circuits Conference

Author(s): T. Toifl ; C. Menolfi ; P. Buchmann ; M. Kossel ; T. Morf ; R. Reutemann ; M. Ruegg ; M. Schmatz ; J. Weiss
Sponsor(s): IEEE Solid-State Circuits Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: San Francisco, CA, USA
Conference Date: 10 February 2005
Page Count: 3
ISBN (Paper): 0-7803-8904-2
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.2005.1494043
Regular:

A PLL generates 8 equidistant clock phases whose timing with respect to a reference clock can be simultaneously shifted in 3ps steps by a digital value. Each VCO phase is fed to a dedicated phase... View More

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