IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 50 MS/s (35 mW) to 1 kS/s (15 /spl mu/W) power scaleable 10b pipelined ADC with minimal bias current variation

2005 IEEE International Solid-State Circuits Conference

Author(s): I. Ahmed ; D. Johns
Sponsor(s): IEEE Solid-State Circuits Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: San Francisco, CA, USA
Conference Date: 10 February 2005
Page Count: 3
ISBN (Paper): 0-7803-8904-2
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.2005.1493978
Regular:

A new opamp with a short power-on time is used in a 10b 1.5b/stage power scalable pipelined ADC in 0.18 /spl mu/m CMOS. A current modulation technique is used so that as the power is varied from... View More

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