IEEE - Institute of Electrical and Electronics Engineers, Inc. - Copper via chain under etching process improvement

2005 IEEE International Reliability Physics Symposium. Proceedings 43rd Annual

Author(s): J. Ji ; M. Zhang ; W. Dong ; A. Guo ; S. Liang ; S. Liao ; C. Niou ; K. Chien
Sponsor(s): IEEE Electron Devices Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: San Jose, CA, USA, USA
Conference Date: 17 April 2005
Page Count: 2
Page(s): 688 - 689
ISBN (Paper): 0-7803-8803-8
DOI: 10.1109/RELPHY.2005.1493206
Regular:

Via under etching is one of the Cu dual damascene process related concerns. This paper presents our findings of localized via chain under etching and the proces improvement on the WAT (wafer... View More

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