IEEE - Institute of Electrical and Electronics Engineers, Inc. - Process optimization of lead-free wafer-level underfill material used in chip scale packaging

2005. 10th International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces

Author(s): Y. Liu ; G. Dutt ; A. Xiao
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Irvine, CA, USA, USA
Conference Date: 16 March 2005
Page Count: 5
Page(s): 293 - 297
ISBN (Paper): 0-7803-9085-7
ISBN (Online): 0-7803-9086-5
ISSN (Paper): 1550-5723
DOI: 10.1109/ISAPM.2005.1432092
Regular:

Wafer-level underfilling is an emerging technology that consists of pre-applying the underfill material on wafer during the wafer fabrication process. The novel underfill material and the process... View More

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