IEEE - Institute of Electrical and Electronics Engineers, Inc. - Store buffer design in first-level multibanked data caches

Proceedings. 32nd International Symposium on Computer Architecture

Author(s): E.F. Torres ; P. Ibanez ; V. Vinals ; J.M. Llaberia
Sponsor(s): IEEE Comput. Soc. Tech. Comm. on Comput. Archit. ACM SIGARCH
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Madison, WI, USA, USA
Conference Date: 4 June 2005
Page(s): 469 - 480
ISBN (Paper): 0-7695-2270-X
ISSN (Paper): 1063-6897
DOI: 10.1109/ISCA.2005.47
Regular:

This paper focuses on how to design a store buffer (STB) well suited to first-level multibanked data caches. Our goal is to forward data from in-flight stores to dependent loads with the latency... View More

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