IEEE - Institute of Electrical and Electronics Engineers, Inc. - Adaptive mechanisms and policies for managing cache hierarchies in chip multiprocessors

Proceedings. 32nd International Symposium on Computer Architecture

Author(s): E. Speight ; H. Shafi ; Lixin Zhang ; R. Rajamony
Sponsor(s): IEEE Comput. Soc. Tech. Comm. on Comput. Archit. ACM SIGARCH
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Madison, WI, USA, USA
Conference Date: 4 June 2005
Page(s): 346 - 356
ISBN (Paper): 0-7695-2270-X
ISSN (Paper): 1063-6897
DOI: 10.1109/ISCA.2005.8
Regular:

With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor cores, varying... View More

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