IEEE - Institute of Electrical and Electronics Engineers, Inc. - Reducing the communication bottleneck via on-chip cosimulation of gate-level HDL and C-models on a hardware accelerator

Proceedings. IEEE Computer Society Annual Symposium on VLSI

Author(s): A. Maili ; C. Steger ; R. Weib ; R. Quigley ; D. Dalton
Sponsor(s): IEEE Comput. Soc. Tech. Comm. on VLSI
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Tampa, FL, USA
Conference Date: 11 May 2005
Page(s): 290 - 291
ISBN (Paper): 0-7695-2365-X
DOI: 10.1109/ISVLSI.2005.61
Regular:

This paper presents a hardware acceleration system based on a gate-level accelerator and an on-chip microprocessor enabling co-simulation of C-models with gate-level modules on the accelerator.... View More

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