IEEE - Institute of Electrical and Electronics Engineers, Inc. - Synthesis of self-resetting stage logic pipelines

Proceedings. IEEE Computer Society Annual Symposium on VLSI

Author(s): Abdelhalim Alsharqawi ; Abdel Ejnioui
Sponsor(s): IEEE Comput. Soc. Tech. Comm. on VLSI
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Tampa, FL, USA
Conference Date: 11 May 2005
Page(s): 260 - 262
ISBN (Paper): 0-7695-2365-X
DOI: 10.1109/ISVLSI.2005.70
Regular:

In this paper, a methodology to synthesize SRSL pipelines has been presented. The synthesis of SRSL pipelines is formulated as an integer programming (IP) problem subject to area and timing... View More

Advertisement