IEEE - Institute of Electrical and Electronics Engineers, Inc. - Post-placement pin optimization

Proceedings. IEEE Computer Society Annual Symposium on VLSI

Author(s): J. Westra ; P. Groeneveld
Sponsor(s): IEEE Comput. Soc. Tech. Comm. on VLSI
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Tampa, FL, USA
Conference Date: 11 May 2005
Page(s): 238 - 243
ISBN (Paper): 0-7695-2365-X
DOI: 10.1109/ISVLSI.2005.57
Regular:

Pin assignment is the process of placing pins on the boundary of a chip or macro during chip design. Problem is that cell placement and pin assignment form a chicken and egg problem: cell... View More

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