IEEE - Institute of Electrical and Electronics Engineers, Inc. - A nonlinear programming based power optimization methodology for gate sizing and voltage selection

Proceedings. IEEE Computer Society Annual Symposium on VLSI

Author(s): V. Mahalingam ; N. Ranganathan
Sponsor(s): IEEE Comput. Soc. Tech. Comm. on VLSI
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Tampa, FL, USA
Conference Date: 11 May 2005
Page(s): 180 - 185
ISBN (Paper): 0-7695-2365-X
DOI: 10.1109/ISVLSI.2005.12
Regular:

In this paper, we investigate the problem of power optimization in CMOS circuits using gate sizing and voltage selection for a given clock period specification. Several solutions have been... View More

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