IEEE - Institute of Electrical and Electronics Engineers, Inc. - 409ps 4.7 FO4 64b adder based on output prediction logic in 0.18um CMOS

Proceedings. IEEE Computer Society Annual Symposium on VLSI

Author(s): Sheng Sun ; Yi Han ; Xinyu Guo ; Kian Haur Chong ; L. McMurchie ; C. Sechen
Sponsor(s): IEEE Comput. Soc. Tech. Comm. on VLSI
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Tampa, FL, USA
Conference Date: 11 May 2005
Page(s): 52 - 58
ISBN (Paper): 0-7695-2365-X
DOI: 10.1109/ISVLSI.2005.2
Regular:

We present a fast 64b adder based on output prediction logic (OPL) that has a measured worst-case delay of 409ps, equivalent to 4.7 FO4 inverter delays for the TSMC 0.18/spl mu/m process that was... View More

Advertisement