IEEE - Institute of Electrical and Electronics Engineers, Inc. - An instruction-level analytical power model for designing the low power systems on a chip

2005 6th International Conference on ASIC Proceedings

Author(s): Rong Luo ; Hong Luo ; Huazhong Yang ; Yuan Xie
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Shanghai, China
Conference Date: 24 October 2005
Volume: 2
Page(s): 1,094 - 1,097
ISBN (Paper): 0-7803-9210-8
DOI: 10.1109/ICASIC.2005.1611515
Regular:

In this paper, an instruction-level analytical power model for the low power systems on a chip (SoC) is proposed. The inter-instruction effects are obtained with combining different instructions... View More

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