IEEE - Institute of Electrical and Electronics Engineers, Inc. - Area optimization in deep sub-micron VLSI design

2005 6th International Conference on ASIC Proceedings

Author(s): Wang Dong-Hui ; Yu Qian ; Liu Yan
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Shanghai, China
Conference Date: 24 October 2005
Volume: 2
Page(s): 797 - 800
ISBN (Paper): 0-7803-9210-8
DOI: 10.1109/ICASIC.2005.1611448
Regular:

Area is an important factor in deep sub-micron VLSI design. In order to save die size during back-end design for our DSP microprocessor - SuperV, double metal power rings were designed, and some... View More

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