IEEE - Institute of Electrical and Electronics Engineers, Inc. - A low-voltage low-power CMOS sample-and-hold circuit

2005 6th International Conference on ASIC Proceedings

Author(s): Zheng Xiao-yan ; Guo Shu-bao ; Wang Jiang ; Qiu Yu-lin
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Shanghai, China
Conference Date: 24 October 2005
Volume: 2
Page(s): 534 - 538
ISBN (Paper): 0-7803-9210-8
DOI: 10.1109/ICASIC.2005.1611388
Regular:

A low power supply sample-and-hold circuit for a pipelined analog-to-digital converter is described. Several approaches have been used to reduce the power consumption, including a gain-compensated... View More

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