IEEE - Institute of Electrical and Electronics Engineers, Inc. - High-performance and low-voltage challenges for sub-45nm microprocessor circuits

2005 6th International Conference on ASIC Proceedings

Author(s): R.K. Krishnamurthy ; S.K. Mathew ; M.A. Anders ; S.K. Hsu ; H. Kaul ; S. Borkar
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Shanghai, China
Conference Date: 24 October 2005
Volume: 1
Page(s): 283 - 286
ISBN (Paper): 0-7803-9210-8
DOI: 10.1109/ICASIC.2005.1611299
Regular:

Increasingly aggravated challenges in CMOS technology scaling beyond the 45nm node has resulted in several new design paradigm shifts necessary for high-performance and low-power microprocessors.... View More

Advertisement