IEEE - Institute of Electrical and Electronics Engineers, Inc. - Local-damascene-finFET DRAM integration with p/sup +/ doped poly-silicon gate technology for sub-60nm device generations

International Electron Devices Meeting 2005

Author(s): Yong-Sung Kim ; Sang-Hyeon Lee ; Soo-Ho Shin ; Sung-Hee Han ; Ju-Yong Lee ; Jin-Woo Lee ; Jun Han ; Seung-Chul Yang ; Joon-Ho Sung ; Eun-Cheol Lee ; Bo-Young Song ; Dong-Jun Lee ; Dong-Il Bae ; Won-Suk Yang ; Yang-Keun Park ; Kyu-Hyun Lee ; Byung-Hyuk Roh ; Tae-Young Chung ; Kinam Kim ; Wonshik Lee
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Washington, DC, USA
Conference Date: 5 December 2005
Page Count: 4
Page(s): 315 - 318
ISBN (Paper): 0-7803-9268-X
DOI: 10.1109/IEDM.2005.1609338
Regular:

We integrate FinFET DRAM in sub-60nm feature size. To avoid severe passing gate effects in FinFET cell array, we introduce a local damascene gate structure. Threshold voltage control of the ultra... View More

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