IEEE - Institute of Electrical and Electronics Engineers, Inc. - An advanced low power, high performance, strained channel 65nm technology

International Electron Devices Meeting 2005

Author(s): S. Tyagi ; C. Auth ; P. Bai ; G. Curello ; H. Deshpande ; S. Gannavaram ; O. Golonzka ; R. Heussner ; R. James ; C. Kenyon ; S.-H. Lee ; N. Lindert ; M. Liu ; R. Nagisetty ; S. Natarajan ; C. Parker ; J. Sebastian ; B. Sell ; S. Sivakumar ; A. St Amour ; K. Tone
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Washington, DC, USA
Conference Date: 5 December 2005
Page Count: 3
Page(s): 245 - 247
ISBN (Paper): 0-7803-9268-X
DOI: 10.1109/IEDM.2005.1609318
Regular:

An advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented. At 1V and off current of 100nA/mum, transistors have record currents of... View More

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