IEEE - Institute of Electrical and Electronics Engineers, Inc. - High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL

International Electron Devices Meeting 2005

Author(s): W.-H. Lee ; A. Waite ; H. Nii ; H.M. Nayfeh ; V. McGahay ; H. Nakayama ; D. Fried ; H. Chen ; L. Black ; R. Bolam ; J. Cheng ; D. Chidambarrao ; C. Christiansen ; M. Cullinan-Scholl ; D.R. Davies ; A. Domenicucci ; P. Fisher ; J. Fitzsimmons ; J. Gill ; M. Gribelyuk ; D. Harmon ; J. Holt ; K. Ida ; M. Kiene ; J. Kluth ; C. Labelle ; A. Madan ; K. Malone ; P.V. McLaughlin ; M. Minami ; D. Mocuta ; R. Murphy ; C. Muzzy ; M. Newport ; S. Panda ; I. Peidous ; A. Sakamoto ; T. Sato ; G. Sudo ; H. VanMeer ; T. Yamashita ; H. Zhu ; P. Agnello ; G. Bronner ; G. Freeman ; S.-F. Huang ; T. Ivers ; S. Luning ; K. Miyamoto ; H. Nye ; J. Pellerin ; K. Rim ; D. Schepis ; T. Spooner ; X. Chen ; M. Khare ; M. Horstmann ; A. Wei ; T. Kammler ; J. Hontschel ; H. Bierstedt ; H.-J. Engelmann ; A. Hellmich ; K. Hempel ; G. Koerner ; A. Neu ; R. Otterbach ; C. Reichel ; M. Trentsch ; P. Press ; K. Frohberg ; M. Schaller ; H. Salz ; J. Hohage ; H. Ruelke ; J. Klais ; M. Raab ; D. Greenlaw ; N. Kepler
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Washington, DC, USA
Conference Date: 5 December 2005
Page Count: 4
ISBN (Paper): 0-7803-9268-X
DOI: 10.1109/IEDM.2005.1609265
Regular:

A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL... View More

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