IEEE - Institute of Electrical and Electronics Engineers, Inc. - Topography Simulation for Wafer-scale Structural Analysis

2005 International Semiconductor Device Research Symposium

Author(s): Jun-Gu Lee ; Taeyoung Won
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Bethesda, MD, USA
Conference Date: 7 December 2005
Page Count: 2
Page(s): 382 - 383
ISBN (Paper): 1-4244-0083-X
DOI: 10.1109/ISDRS.2005.1596146
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