IEEE - Institute of Electrical and Electronics Engineers, Inc. - Deposition and electrical characterisation of a MOS memory structure containing AU nanoparticles in a high-k dielectric layer

2005 International Semiconductor Device Research Symposium

Author(s): Ch. Sargentis ; K. Giannakopoulos ; A. Travlos ; D. Tsamakis ; G. Krokidis
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Bethesda, MD, USA
Conference Date: 7 December 2005
Page Count: 2
Page(s): 342 - 343
ISBN (Paper): 1-4244-0083-X
DOI: 10.1109/ISDRS.2005.1596126
Regular:

In this work, we use the MBE method in order to fabricate MOS memory devices with gold (Au) nanoparticles embedded on a SiO2/HfO2 interface. We have chosen to work with Au... View More

Advertisement