IEEE - Institute of Electrical and Electronics Engineers, Inc. - Artificial dislocation network for Si nanodevices

Digest of Papers Microprocesses and Nanotechnology 2005. 2005 International Microprocesses and Nanotechnology Conference

Author(s): Y. Ishikawa ; M. Tabe
Sponsor(s): Japan Soc. of Appl. Phys
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Tokyo, Japan, Japan
Conference Date: 25 October 2005
Page(s): 60 - 61
ISBN (Paper): 4-9902472-2-1
DOI: 10.1109/IMNC.2005.203737
Regular:

With the use of SOI structure, formation of a nanometer-scale potential array is the key issue for the multi-junction SET/SHT devices. In this talk, a 2D dislocation network artificially embedded... View More

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