IEEE - Institute of Electrical and Electronics Engineers, Inc. - Clock-tree routing with single buffer-block allocation strategy

2005 48th IEEE International Midwest Symposium on Circuits and Systems

Author(s): Chuen-Yau Chen ; Pei-Chia Yang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Covington, KY, USA
Conference Date: 7 August 2005
Page Count: 4
ISBN (Paper): 0-7803-9197-7
DOI: 10.1109/MWSCAS.2005.1594385
Regular:

In this paper, we propose a method combining the concepts of buffer-insertion with global-routing to build a zero-skew clock tree with less latency. First, we allocate a single buffer-block for... View More

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