IEEE - Institute of Electrical and Electronics Engineers, Inc. - Minimization of secondary effects in SOI: a 32-bit ANT logic adder implementation

2005 48th IEEE International Midwest Symposium on Circuits and Systems

Author(s): A. Wasson ; Dipti Sanghvi ; A. Nunez
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Covington, KY, USA
Conference Date: 7 August 2005
Page Count: 4
ISBN (Paper): 0-7803-9197-7
DOI: 10.1109/MWSCAS.2005.1594082
Regular:

This paper presents a review of circuit design techniques related to silicon on insulator technology (SOI) CMOS circuits. The most important design considerations are parasitic bipolar effect,... View More

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