IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design and Development of Interconnects for Ultra-Fine Pitch Wafer Level Packages

2005 6th International Conference on Electronics Packaging Technology

Author(s): A.A.O. Tay ; M.K. Iyer ; R.R. Tummala
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Shenzhen, China
Conference Date: 30 August 2005
Page(s): 1 - 8
ISBN (Paper): 0-7803-9449-6
DOI: 10.1109/ICEPT.2005.1564732
Regular:

According to the latest ITRS roadmap, the pitch of area array packages is expected to decrease to 100 mum by 2009. Simultaneously, the electrical performance of these interconnections needs to be... View More

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