IEEE - Institute of Electrical and Electronics Engineers, Inc. - High-density logic techniques with reduced-stack double-gate MOSFETs

2005 IEEE International SOI Conference

Author(s): Meng-Hsueh Chiang ; Keunwoo Kim ; Ching-Te Chuang ; C. Tretz
Sponsor(s): IEEE Electron. Dev. Soc
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Honolulu, HI, USA
Conference Date: 3 October 2005
Page(s): 85 - 86
ISBN (Paper): 0-7803-9212-4
ISSN (Paper): 1078-621X
DOI: 10.1109/SOI.2005.1563544
Regular:

We have presented a high-density DG logic circuit technique exploiting the unique V/sub T/ modulation effect through the extended gate-to-gate coupling in high-V/sub T/ symmetrical DG devices. The... View More

Advertisement