IEEE - Institute of Electrical and Electronics Engineers, Inc. - A compiler-controlled instruction cache architecture for an embedded low power microprocessor

The Fifth International Conference on Computer and Information Technology CIT 2005

Author(s): Xiaoping Zhu ; T.T. Tay
Sponsor(s): Univ. of Aizu, Japan
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2005
Conference Location: Shanghai, China
Conference Date: 21 September 2005
Page(s): 815 - 821
ISBN (Paper): 0-7695-2432-X
DOI: 10.1109/CIT.2005.3
Regular:

Modern microprocessors have been improving their performance with deeper sub-micron technologies and larger on-chip cache memories. This trend leads to a dramatic increment of power consumption in... View More

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