IEEE - Institute of Electrical and Electronics Engineers, Inc. - Simultaneous buffer and wire sizing for performance and power optimization

Proceedings of 1996 International Symposium on Low Power Electronics and Design

Author(s): Cong, J. ; Cheng-Kok Koh ; Kwok-Shing Leung
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1996
Conference Location: Monterey, CA, USA, USA
Conference Date: 12 August 1996
Page(s): 271 - 276
ISBN (Paper): 0-7803-3571-6
DOI: 10.1109/LPE.1996.547521
Regular:

In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions. This relation... View More

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