IEEE - Institute of Electrical and Electronics Engineers, Inc. - A novel methodology for transistor-level power estimation [CMOS circuits]

Proceedings of 1996 International Symposium on Low Power Electronics and Design

Author(s): Shi-Yu Huang ; Kwang-Ting Cheng ; Kuang-Chien Chen ; Lee, M.T.-C.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1996
Conference Location: Monterey, CA, USA, USA
Conference Date: 12 August 1996
Page(s): 67 - 72
ISBN (Paper): 0-7803-3571-6
DOI: 10.1109/LPE.1996.542732
Regular:

Transistor-level power simulators, which are more accurate than logic-level power estimators, are popular to estimate the power dissipation of CMOS circuits. We introduce a method which extends... View More

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