IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 0.5 V/100 MHz over-V/sub CC/ grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes

Proceedings of 1996 International Symposium on Low Power Electronics and Design

Author(s): Yamauchi, H. ; Iwata, T. ; Akamatsu, H. ; Matsuzawa, A.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1996
Conference Location: Monterey, CA, USA, USA
Conference Date: 12 August 1996
Page(s): 49 - 54
ISBN (Paper): 0-7803-3571-6
DOI: 10.1109/LPE.1996.542729
Regular:

This paper proposes a 0.5 V/100 MHz/sub-5 mW-operated 1-Mbit SRAM cell architecture which uses an over-V/sub CC/ grounded data storage (OVGS) scheme. The key target of OVGS is to minimize the... View More

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