IEEE - Institute of Electrical and Electronics Engineers, Inc. - Post-layout optimization for deep submicron design

Proceedings of 33rd Design Automation Conference

Author(s): Sato, K. ; Kawarabayashi, M. ; Emura, H. ; Maeda, N.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1996
Conference Location: Las Vegas, NV, USA, USA
Conference Date: 3 June 1996
Page(s): 740 - 745
ISBN (Paper): 0-7803-3294-6
ISSN (Paper): 0738-100X
DOI: 10.1109/DAC.1996.545671
Regular:

To reduce the number of synthesis and layout iterations, we present a new delay optimization technique, which inserts buffers based on back-annotated detailed routing information. During... View More

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