IEEE - Institute of Electrical and Electronics Engineers, Inc. - Innovative verification strategy reduces design cycle time for high-end SPARC processor

Proceedings of 33rd Design Automation Conference

Author(s): Popescu, V. ; McNamara, B.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1996
Conference Location: Las Vegas, NV, USA, USA
Conference Date: 3 June 1996
Page(s): 311 - 314
ISBN (Paper): 0-7803-3294-6
ISSN (Paper): 0738-100X
DOI: 10.1109/DAC.1996.545592
Regular:

Superscalar processor developers are creatively leveraging best-in-class design verification tools to meet narrow market windows. Accelerated simulation is especially useful owing to its... View More

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