IEEE - Institute of Electrical and Electronics Engineers, Inc. - Evaluation of fault-tolerant designs implemented on SRAM-based FPGAs

Proceedings. 10th IEEE Pacific Rim International Symposium on Dependable Computing

Author(s): G. Asadi ; S.G. Miremadi ; H.R. Zarandi ; A. Ejlali
Sponsor(s): IEEE Comput. Soc. Tech. Committee on Fault Tolerant Comput.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2004
Conference Location: Papeete, Tahiti, French Polynesia, French Polynesia
Conference Date: 3 March 2004
Page Count: 6
Page(s): 327 - 332
ISBN (Paper): 0-7695-2076-6
DOI: 10.1109/PRDC.2004.1276583
Regular:

The technology of SRAM-based devices is sensible to single event upsets (SEUs) that may be induced mainly by high energy heavy ions and neutrons. We present a framework for the evaluation of... View More

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