IEEE - Institute of Electrical and Electronics Engineers, Inc. - RTL processor synthesis for architecture exploration and implementation

Proceedings. Design, Automation and Test in Europe Conference and Exhibition

Author(s): O. Schliebusch ; A. Chattopadhyay ; R. Leupers ; G. Ascheid ; H. Meyr ; M. Steinert ; G. Braun ; A. Nohl
Sponsor(s): EDAA, EDA Consortium, IEEE Comput. Soc. TTTC
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2004
Conference Location: Paris, France, France
Conference Date: 16 February 2004
Volume: 3
Page Count: 5
ISBN (Paper): 0-7695-2085-5
ISSN (Paper): 1530-1591
DOI: 10.1109/DATE.2004.1269223
Regular:

Architecture description languages are widely used to perform architecture exploration for application-driven designs, whereas the RT-level is the commonly accepted level for hardware... View More

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