IEEE - Institute of Electrical and Electronics Engineers, Inc. - Time-energy design space exploration for multi-layer memory architectures

Proceedings. Design, Automation and Test in Europe Conference and Exhibition

Author(s): R. Szymanek ; F. Catthoor ; K. Kuchcinski
Sponsor(s): EDAA, EDA Consortium, IEEE Comput. Soc. TTTC
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2004
Conference Location: Paris, France, France
Conference Date: 16 February 2004
Volume: 1
Page Count: 6
ISBN (Paper): 0-7695-2085-5
ISSN (Paper): 1530-1591
DOI: 10.1109/DATE.2004.1268867
Regular:

This paper presents an exploration algorithm which examines execution time and energy consumption of a given application, while considering a parameterized memory architecture. The input to our... View More

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