IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

IEEE International Electron Devices Meeting 2003

Author(s): T. Ghani ; M. Armstrong ; C. Auth ; M. Bost ; P. Charvat ; G. Glass ; T. Hoffmann ; K. Johnson ; C. Kenyon ; J. Klaus ; B. McIntyre ; K. Mistry ; A. Murthy ; J. Sandford ; M. Silberstein ; S. Sivakumar ; P. Smith ; K. Zawadzki ; S. Thompson ; M. Bohr
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2003
Conference Location: Washington, DC, USA, USA
Conference Date: 8 December 2003
Page Count: 3
ISBN (Paper): 0-7803-7872-5
DOI: 10.1109/IEDM.2003.1269442
Regular:

This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers. The unique strained PMOS transistor structure... View More

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