IEEE - Institute of Electrical and Electronics Engineers, Inc. - Ultra-low thermal budget CMOS process for 65nm-node low-operation-power applications

IEEE International Electron Devices Meeting 2003

Author(s): F. Ootsuka ; H. Ozaki ; T. Sasaki ; K. Yamashita ; H. Takada ; N. Izumi ; Y. Nakagawa ; M. Hayashi ; K. Kiyono ; M. Yasuhira ; T. Arikado
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2003
Conference Location: Washington, DC, USA, USA
Conference Date: 8 December 2003
Page Count: 4
ISBN (Paper): 0-7803-7872-5
DOI: 10.1109/IEDM.2003.1269364
Regular:

This paper describes the fabrication process and the performance of 65 nm-node CMOS transistors which have ultra-shallow junctions. Flash lamp annealing enhances the drivability of pFETs with a... View More

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