IEEE - Institute of Electrical and Electronics Engineers, Inc. - Soft error immune 0.46 /spl mu/m/sup 2/ SRAM cell with MIM node capacitor by 65 nm CMOS technology for ultra high speed SRAM

IEEE International Electron Devices Meeting 2003

Author(s): Soon-Moon Jung ; Hoon Lim ; Wonseok Cho ; Hoosung Cho ; Hatae Hong ; Jaehun Jeong ; Sugwoo Jung ; Hanbyung Park ; Byoungkeun Son ; Youngchul Jang ; Kinam Kim
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2003
Conference Location: Washington, DC, USA, USA
Conference Date: 8 December 2003
Page Count: 4
ISBN (Paper): 0-7803-7872-5
DOI: 10.1109/IEDM.2003.1269281
Regular:

The smallest SRAM cell, 0.46 um/sup 2/, is realized by a single pitch cell layout, gate poly trim mask technique, 80 nm contact holes formed by polymer attaching process, and a 193 nm ArF... View More

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