IEEE - Institute of Electrical and Electronics Engineers, Inc. - Scalability of strained silicon CMOSFET and high drive current enhancement in the 40 nm gate length technology

IEEE International Electron Devices Meeting 2003

Author(s): T. Sanuki ; A. Oishi ; Y. Morimasa ; S. Aota ; T. Kinoshita ; R. Hasumi ; Y. Takegawa ; K. Isobe ; H. Yoshimura ; M. Iwai ; K. Sunouchi ; T. Noguchi
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2003
Conference Location: Washington, DC, USA, USA
Conference Date: 8 December 2003
Page Count: 4
ISBN (Paper): 0-7803-7872-5
DOI: 10.1109/IEDM.2003.1269167
Regular:

In this work, we investigated the scalability of strained Si technology. The impact of scaling source/drain length (L/sub SD/) on electrical characteristics was studied for the first time. Drive... View More

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