IEEE - Institute of Electrical and Electronics Engineers, Inc. - Taylor expansion diagrams: a new representation for RTL verification

Proceedings Sixth IEEE International High-Level Design Validation and Test Workshop

Author(s): M. Ciesielski ; P. Kalla ; Zhihong Zeng ; B. Rouzeyre
Sponsor(s): IEEE Comput. Soc. Tech. Council on Test Technol. IEEE Comput. Soc. Tech. Committee on Design Autom
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2001
Conference Location: Monterey, CA, USA, USA
Conference Date: 9 November 2001
Page Count: 6
Page(s): 70 - 75
ISBN (Paper): 0-7695-1411-1
DOI: 10.1109/HLDVT.2001.972810
Regular:

A new, compact, canonical representation for arithmetic expressions, called Taylor expansion diagram, is presented. This representation is based on a non-binary decomposition principle. It treats... View More

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