IEEE - Institute of Electrical and Electronics Engineers, Inc. - Power optimization of standard cell flip flops

Proceedings 13th Annual IEEE International ASIC/SOC Conference

Author(s): Rasmussen, B. ; Wright, J.A.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2000
Conference Location: Arlington, VA, USA
Conference Date: 16 September 2000
Page(s): 315 - 318
ISBN (Paper): 0-7803-6598-4
DOI: 10.1109/ASIC.2000.880756
Regular:

Flip-flops are not normally considered when the analysis of chip power is made for a deep-submicron circuit. When the gate counts get above 250,000, the flip-flop and associated clock trees then... View More

Advertisement