IEEE - Institute of Electrical and Electronics Engineers, Inc. - A balanced approach to high-level verification: performance trade-offs in verifying large-scale multiprocessors
Proceedings of the 2000 International Conference on Parallel Processing
Author(s): | Abts, D. ; Roberts, M. ; Lilja, D.J. |
Publisher: | IEEE - Institute of Electrical and Electronics Engineers, Inc. |
Publication Date: | 1 January 2000 |
Conference Location: | Toronto, Ontario, Canada, Canada |
Conference Date: | 21 August 2000 |
Page(s): | 505 - 510 |
ISBN (Paper): | 0-7695-0768-9 |
ISSN (Paper): | 0190-3918 |
DOI: | 10.1109/ICPP.2000.876167 |
Regular:
A single node of a modern scalable multiprocessor consists of several ASICs comprising tens of millions of gates. This level of integration and complexity imposes an enormous onus on the... View More