IEEE - Institute of Electrical and Electronics Engineers, Inc. - A parametric study of the effects of process parameters on the assembly of chip scale packages

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces

Author(s): Nguty, T.A. ; Salam, B. ; Ekere, N.N.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2000
Conference Location: Braselton, GA, USA
Conference Date: 8 August 2000
Page(s): 208 - 210
ISBN (Paper): 0-930815-59-9
DOI: 10.1109/ISAPM.2000.869272
Regular:

Chip scale packaging (CSP) technology is developing in response to some of the limitations of flip chip technology. It addresses the concerns and perceived risk associated with handling and... View More

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